Alex Clunan

Spring 2026 | 45 nm CMOS

Nine time-interleaved SAR sub-channels in Cadence at 2 GS/s. Bootstrapped sample-and-hold, PMOS-input StrongARM comparator, and a 4+4 segmented CDAC that cut array capacitance ~32× versus binary-weighted. 5.58 ENOB and 42.2 dBc SFDR near Nyquist.

• Cadence Virtuoso
• Data converters
• FFT characterization

Spring 2025 | FreePDK45

Custom 6T array with StrongARM sense amps (28× faster read than a 13T latch) and selective wordline overvolting on the far columns. Best energy × delay² × area × idle-power figure of merit of any project reviewed from prior course offerings; verified at 625 MHz across PVT.

• Cadence
• SPICE
• VLSI

HooHacks 2026 | 3rd of 220+ teams

Raspberry Pi device that listens to phone calls, scores scam risk with an LLM in real time, and alerts family through a Nest speaker, LEDs, and a Next.js dashboard. Full hardware and AI pipeline in 24 hours.

• Raspberry Pi
• FastAPI
• Next.js
• Auth0

2025 | PYNQ-Z1

Two-way encrypted text radio between two Xilinx boards. AES IP generated with Vitis HLS and integrated over AXI with a C driver.

• Vitis HLS
• AXI
• FPGA

Spring 2025 | Verilog

Soft-core CPU with arithmetic, logic, memory, branch, and jump instructions plus an integrated UART transceiver, verified with HDL testbenches and an assembly program in ModelSim.

• Verilog
• RISC-V
• ModelSim

Personal | iCE40

Pong written from scratch in Verilog with pushbutton paddles and VGA output, alongside a set of small iCE40 Go Board experiments in VHDL.

• Verilog
• VGA
• iCE40